//system ctl moudle
//Author:Liuhao
//Date:04,05.2018

/********************************************************************/

module	sys_ctl(
	ext_clk,
	ext_rst,
	sys_clk_130m,
	sys_clk_65m,
	sys_clk_50m,
	sys_clk_25m,
	sys_rst_n
);

input	ext_clk;
input	ext_rst;
	
output	sys_clk_130m;
output	sys_clk_65m;
output	sys_clk_50m;
output	sys_clk_25m;
output	reg sys_rst_n;

/************************************************/
wire	pll_130m;
wire	pll_65m;
wire	pll_50m;

wire	pll_locked;

/************************************************/
assign	sys_clk_130m = pll_130m;
assign	sys_clk_65m = pll_65m;
assign	sys_clk_50m = pll_50m;
assign	sys_clk_25m = pll_25m;

/************************************************/
//sync ext_rst
reg	ext_rst_r1,ext_rst_r2;
reg	sys_rst_nr;

always @ (posedge ext_clk or negedge ext_rst)
begin
	if(!ext_rst)
		ext_rst_r1 <= 1'b0;
	else
		ext_rst_r1 <= 1'b1;
end

always @ (posedge ext_clk or negedge ext_rst)
begin
	if(!ext_rst)
		ext_rst_r2 <= 1'b0;
	else
		ext_rst_r2 <= ext_rst_r1;
end

/************************************************/
//instance of pll
pll	pll_inst(
	.areset(!ext_rst_r2),
	.inclk0(ext_clk),
	.c0(pll_130m),
	.c1(pll_65m),
	.c2(pll_50m),
	.c3(pll_25m),
	.locked(pll_locked)
);

/************************************************/
always @ (posedge pll_130m)
begin
	if(!pll_locked)
		sys_rst_nr <= 1'b0;
	else
		sys_rst_nr <= 1'b1;
end

always @ (posedge pll_130m or negedge sys_rst_nr)
begin
	if(!sys_rst_nr)
		sys_rst_n <= 1'b0;
	else
		sys_rst_n <= sys_rst_nr;
end



endmodule
/********************************************************************/

